1. Field of the Invention
This invention relates generally to semiconductor integrated circuits and, more particularly, to a race free and technology independent flag generating circuit associated with two asynchronous clocks.
2. Description of the Related Art
Frequently, two independent systems are required to communicate with each other. Each system has its own clock and, thus, the two systems are usually asynchronous since they each operate at their own clock rate. Often, flags are employed to synchronize the communications between these asynchronous systems.
Flags signal the present condition of a system resource, process state or any other system parameter and are particularly useful when asynchronous systems share a resource or need to synchronize performed tasks. For example, one system may write into a data buffer while the second system will read out of this same data buffer. It is important to synchronize the access to this data buffer to ensure that the correct information is written to or read out of the buffer. The flag is considered an asynchronous flag since it is derived from the asynchronous systems.
FIG. 1 illustrates an example of how systems with asynchronous clocks utilize a flag to synchronize tasks performed by each of the systems. In this example, Task A and Task B cannot be run at the same time and system 1 and system 2 are running in parallel. To prevent system 1 from performing Task A while system 2 is performing Task B, system 1 will only perform Task A (step 12) when it determines that the FLAG is reset (step 10). In this example, a reset FLAG indicates that system 2 is not performing Task B. Once Task A is performed, system 1 will set the FLAG (step 14). In this example, a set FLAG indicates that system 1 is not performing Task A. To prevent system 2 from performing Task B while system 1 is performing Task A, system 2 will only perform Task B (step 22) when it determines that the FLAG is set (step 20). Once Task B is performed, system 2 will reset the FLAG (step 24) which would allow system 1 to perform Task A.
The communication between a digital signal processor (DSP) and an external device, by way of a Joint Test Access Group (JTAG) port is one example of systems with asynchronous clocks. FIG. 2 illustrates a DSP 50 communicating with an external device 60 through a JTAG port 56 residing on the DSP 50. The DSP 50 includes a JTAG interface 54 connected between the JTAG port 56 and a processor 52 for interpreting JTAG signals between the processor 52 and the external device 60.
FIG. 3 illustrates how the DSP 50 and the external device 60 utilize a buffer full flag JFULL to synchronize the reading of, and writing to, a JTAG output buffer JOUT. In this example, the DSP 50 will write to the output buffer JOUT and the external device 60 will read from the output buffer JOUT, but they cannot do so at the same time. To prevent the DSP 50 from writing to the buffer JOUT while the external device 60 is reading from it, the DSP 50 will only write to the buffer JOUT (step 32) when it determines that the buffer full flag JFULL is reset (step 30). In this example, a reset buffer full flag JFULL indicates that the external device has finished reading out the contents of the buffer JOUT. Once the buffer JOUT is written to, the DSP 50 will set the buffer full flag JFULL (step 34). In this example, a set buffer full flag JFULL indicates that the DSP has finished writing into the buffer JOUT. To prevent the external device 60 from reading from the buffer JOUT while the DSP 50 is writing to it, the external device 60 will only read from the buffer JOUT (step 42) when it determines that the buffer fill flag JFULL is set (step 40). Once the buffer JOUT is read from, the external device 60 will reset the buffer fill flag JFULL (step 44) which would allow the DSP 50 to write into the buffer JOUT.
Generally, flags are generated and maintained by flag generating circuitry. This is done so that the asynchronous systems may access the shared resource, synchronize required tasks, etc., without taking steps to set or reset the flag. For example, the DSP 50 may initiate step 34 by simply writing to the output buffer JOUT. The flag generating circuit may use a signal generated by the write operation to set the buffer full flag JFULL. One well known problem that must be compensated for by any flag generating circuit is referred to as a race condition. A race condition occurs when both systems, the DSP 50 and the external device 60, for example, attempt to set or reset the same flag, JFULL, for example, at the same time. Again, this problem arises because the buffer full flag JFULL is being set and reset by two systems with asynchronous clocks. Accordingly, flag generating circuits will often contain "race free" circuitry to avoid race conditions.
FIG. 4 illustrates an exemplary conventional flag generating circuit 70 used to set or reset a flag FLAG while preventing race conditions between the asynchronous signals SETFLAG and RSTFLAG. The circuit 70 is designed to keep the signals SETFLAG, RSTFLAG used to set and reset the flag FLAG very short. Therefore, the circuit 70 creates and uses short pulses to set and reset the flag FLAG. Short pulses are used to lower the probability that two pulses will be generated at the same time (i.e., a race condition between the pulses).
The circuit 70 includes ten inverters 72, 74, 76, 78, 80, 84, 86, 88, 90, 92, two AND gates 82, 94 and an RS latch 96. The output from the non-inverting terminal Q of the latch 96 is used as the flag FLAG. To set the flag FLAG, a set flag signal SETFLAG must be received by the circuit 70. The SETFLAG signal passes through four inverters 74, 76, 78, 80 and is input into the first AND gate 82. The SETFLAG signal also passes through the first inverter 72. The output of the first inverter 72 is input into the first AND gate 82. The output of the first AND gate 82 will be a set flag pulse which is input into the RS latch 96. The length of the set flag pulse is determined by the inverters 72, 74, 76, 78, 80. This set flag pulse will be used to set the flag FLAG output from the latch 96. Likewise, to reset the flag FLAG, a reset flag signal RSTFLAG must be received by the circuit 70. The RSTFLAG signal passes through four inverters 86, 88, 90, 92 and is input into the second AND gate 94. The RSTFLAG signal also passes through the sixth inverter 84. The output of the sixth inverter 84 is input into the second AND gate 94. The output of the second AND gate 94 will be a reset flag pulse which is input into the RS latch 96. The length of the reset flag pulse is determined by the inverters 84, 86, 88, 90, 92. This reset flag pulse will be used to reset the flag FLAG output from the latch 96. The race condition is avoided by using the short pulses to set/reset the flag FLAG.
The pulses used to set and reset the flag FLAG are usually short pulses. Short pulses are used to lower the probability that two pulses will be generated at the same time (i.e., a race condition between the pulses). Unfortunately, the circuit 70 illustrated in FIG. 4 has some shortcomings. For example, the circuit 70 is technology dependent. That is, changes in the types of inverters used in the circuit 70 or the process technology used to manufacture the integrated circuit 70 may cause the lengths of the pulses to change. For example, different sized inverters may cause the length of the pulses to be very short. A very short pulse may not be detected and, thus, the flag may not be set or reset correctly. Conversely, different sized inverters may cause the length of the pulses to be very long. A very long pulse may be treated as two separate pulses which could cause a race condition or other problems. Accordingly, there is a need and desire for a race free and technology independent flag generating circuit capable of setting and resetting flags associated with asynchronous clocks.